The waveform of a digital signal that is output by a transmitter deteriorates while being transmitted from the transmitter to the receiver via a transmission path and a clock signal and data must be restored on the receiver side. The clock data restoration device for performing such restoration is disclosed in Patent Documents 1 and 2, for example.
The device disclosed in these Patent Documents 1 and 2 considers the fact that the time when the data in the digital signal whose waveform deteriorates make the transition changes and detects the data of the respective bits with three timings. Here, among the three timings when detecting the data of the respective bits, the first timing is set close to the start time of the data stability period of the bits, the second timing is set close to the end time of the data stability period of the bits, and a third timing is set at a middle time between the first and second timings.
Further, the device disclosed in Patent Document 1 restores the clock signal by adjusting the respective timings so that all the data detected at the three timings for the respective bits match and, at this time, restores the data by detecting the data of the respective bits at the middle third timing.
However, the device disclosed in Patent Document 2 restores the clock signal by adjusting the respective timings so that the bit error rates at the first timing and second timing respectively (that is, the rate at which the data detected at each of these timings differs from the data detected at the middle third timing) are equal to one another and lie within the start set range and restores data by detecting the data of the respective bits at the middle third timing.    [Patent Document 1] Japanese Application Laid Open No. H7-221800    [Patent Document 2] Japanese Published Patent Application, Japanese Translation of PCT international application No. 2004-507963